The present invention relates to a semiconductor memory and, more particularly, to a technique which is effective when utilized in a dual-port memory having a serial input/output function and a random input/output function for image processing, for example.
As a memory for image processing effective for displaying letters and drawings on the frame of a CRT (i.e., Cathode Ray Tube), there are known in the art, for example, memories which are disclosed on pp. 219 to 229, "NIKKEI ELECTRONICS" published by NIKKEI McGRAW-HILL, on Feb. 11, 1985 and pp. 211 to 240, "NIKKEI ELECTRONICS" published on Aug. 12, 1985.
The former memory transfers the signals of a memory array in parallel to a shift register and outputs them in series, or inputs the signals in series to the shift register and writes them in parallel in the memory array.
On the other hand, the latter memory requires decoder circuits especially for random access and serial output function of a memory array, respectively. Moreover, the serial output function operates such a dynamic latch circuit as an amplifier as will fetch the signals of data of the memory array in parallel and output them in series.